Semiconductor memory devices are widely used in many electronic products. Depending on the field of application, memory cell types having different operating speed and density are desired. For example, static random access memory (SRAM) is optimized for high random access speed, while stand alone dynamic random access memory (DRAM) is optimized for high density but moderate random access speed.
FIG. 5a-c illustrate semiconductor memory cells of prior arts. 1T-1C DRAM cell is shown in FIG. 5a; floating body cell (1T-DRAM) is shown in FIG. 5b; 6T-SRAM cell is shown in FIG. 5c. 
A conventional 1T-1C DRAM cell 500 consists of 1 access transistor 503 and 1 capacitor 504. When operating a 1T-1C DRAM cell, a logic bit can be assigned to a cell, wherein a first logic state of the bit can be assigned to the state with high potential and a second logic state of the bit can be assigned to the memory cell with lower potential. When reading a 1T-1C memory cell, the access transistor 503 is turned on by word line 501. The bit-line voltage will be affected due to charge sharing between the storage capacitor 504 and the bit line 502. Using a voltage sense amplifier, the voltage change of bit line can be sensed and logic state of the DRAM memory cell can be distinguished. DRAM read operation is destructive and a write-back sequence is needed to restore the read bits. Therefore, the random access speed of DRAM is usually lower than 6-T SRAM 520 which does not need the write-back sequence after read operation. In addition, the capacitance of the storage capacitor must not be too low in order to store sufficient charge. Thus, the area of capacitor is difficult to be scaled and the processes for building capacitor add to DRAM manufacturing complexity.
An example 6-transistor (6T) SRAM is shown in FIG. 5c. The cross-coupled inverters are used to store logic state “1” or “0”. Two access NMOS-FETs are used to access the storage nodes. The read operation of SRAM cell is non-destructive. Furthermore, SRAM can have very short time for write and read, e.g. 0.5 nano-second. For these reasons, SRAM is applied in Central Processing Unit (CPU) as L1 and L2 caches. The conventional SRAM cell is formed by 6 transistors, thus it has larger unit cell size compared to DRAM cell which usually has 1 access transistor and 1 capacitor (1T-1C). With the scaling of SRAM, the standby leakage current increases, resulting in an increasing power consumption. In addition, as the circuit scaled, the static noise margin window of 6-T SRAM gets smaller and the stability gets worse. In order to improve the static noise margin and stability, an 8-transistor SRAM cell was proposed by L. Chang, et al. [U.S. patent application: U.S. Pat. No. 7,106,620, B2]. The trade-off of improved stability is increased transistor numbers and therefore larger unit memory cell size.
In order to combine the advantages of SRAM and DRAM into a single memory cell, recently, floating body cell (FBC) memory was proposed by T. Ohsawa[1]. [Takashi Ohsawa et al., “Memory Design Using One-Transistor Gain Cell on SOI”, ISSCC Digest of Technical Papers, 2002, pp. 152-153]. FIG. 5b shows an equivalent circuit for a FBC[2] [U.S. patent application: US 2006/0279985 A1, A. Keshavarzi, et. al.]. This kind of memory cell is formed by a single MOSFET which is usually fabricated on silicon-on-insulator (SOI) substrate. By storing the majority charges in the floating body, the threshold voltage of a MOSFET can be changed. Memory cells with high or low threshold voltage are assigned to logic bit 1 or 0. When reading a cell, a certain voltage is applied and current will flow through the FBC memory cell. Using a sensing circuitry, for example, a current sensor, logic state stored in one FBC (e.g. 0 or 1) can be distinguished.
Compared to the conventional 1T-1C DRAM and 6-T SRAM, the 1T configuration of FBC memory has smaller unit cell size. For FBC, the read operation is quasi non-destructive and the write-back sequence after reading-operation is not mandatory. Therefore, its random access speed can be faster than DRAM and close to SRAM. FBC has potential to become the replacement of SRAM and DRAM in the future. However, FBC usually requires SOI substrate which is usually more expensive than the conventional bulk silicon substrate. In addition, only very limited number of charges are stored in the floating body, as results in poor retention performance. Further, the performance of FBC is quite sensitive to temperature. For instance, the writing speed will be lower and the stored charge will vanish faster at higher operating temperature. There are some methods existing to improve the performance of this kind of memory cell, e.g. an back-bias gate electrode was proposed in addition to the main control gate[3]. [Published Japanese Patent Application No. 2002-246571 and 2003-31693.] However, the junction leakage current in FBC is hard to be scaled when scaling down the FBC cell, the retention performance of FBC is usually much worse than 1T-1C DRAM even with back-gate bias[4]. [IEDM tech. Dig. 2006: Floating Body RAM Technology and its Scalability to 32 nm Node and Beyond, T. Shino. Page: 1-4]
Among the above mentioned three types of semiconductor memory devices, SRAM has the highest speed but the unit cell size is the largest. 1T-1C DRAM has moderate unit cell size and speed. FBC has the smallest unit cell size and simplest structure but the data retention performance is poor. The present invention proposes a different type of semiconductor memory cell which has the advantages of high retention performance, small cell size, and high random access speed.